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                    <article>
                        <h1 class="entry-title"><a href="../new-ubuntu-old-problems-with-modelsim.html">New Ubuntu, old problems with ModelSim</a></h1>
<div class="post-info">
	<ul>
        <li class="vcard author">
                 by&nbsp;<a class="url fn" href="../author/jan-marjanovic.html">Jan Marjanovic</a>
        </li>
        <li class="published" title="2019-04-20T08:40:00+02:00">
          on&nbsp;Sat 20 April 2019
        </li>

	</ul>
<p>Category: <a href="../tag/fpga.html">FPGA</a>, <a href="../tag/modelsim.html">ModelSim</a>, </p>
</div><!-- /.post-info --><p>A couple of days ago a new release of Ubuntu, Ubuntu 19.04 Disco Dingo was
released. On my personal laptop I follow the non-LTS line, which brings
me cool features and updated programs (e.g. Python 3.7, GCC 8.3, ...)
out-of-the-box.</p>
<p>Unfortunately, because the libraries are updated, the …</p>
                    </article>
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                        <h1 class="entry-title"><a href="../chisel-tester-with-overridden-step-method.html">Chisel tester with overridden step() method</a></h1>
<div class="post-info">
	<ul>
        <li class="vcard author">
                 by&nbsp;<a class="url fn" href="../author/jan-marjanovic.html">Jan Marjanovic</a>
        </li>
        <li class="published" title="2018-10-14T21:00:00+02:00">
          on&nbsp;Sun 14 October 2018
        </li>

	</ul>
<p>Category: <a href="../tag/fpga.html">FPGA</a>, <a href="../tag/scala.html">Scala</a>, <a href="../tag/bfm.html">BFM</a>, </p>
</div><!-- /.post-info --><h1>Introduction</h1>
<p><a href="https://chisel.eecs.berkeley.edu/">Chisel</a> is a modern take on Hardware
Description Languages, such as (System)Verilog and VHDL. Both Verilog and VHDL
were conceived in 80s, and are currently still the main two options when it
comes to describing hardware. From the Developer Experience point-of-view, I
would say that both languages are …</p>
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                        <h1 class="entry-title"><a href="../books-read-e-stavinov-100-power-tips-for-fpga-designers.html">Books read: E. Stavinov: 100 Power Tips for FPGA Designers</a></h1>
<div class="post-info">
	<ul>
        <li class="vcard author">
                 by&nbsp;<a class="url fn" href="../author/jan-marjanovic.html">Jan Marjanovic</a>
        </li>
        <li class="published" title="2016-10-18T23:00:00+02:00">
          on&nbsp;Tue 18 October 2016
        </li>

	</ul>
<p>Category: <a href="../tag/fpga.html">FPGA</a>, <a href="../tag/xilinx.html">Xilinx</a>, </p>
</div><!-- /.post-info --><p>I recently found a great book explaining in details FPGA workflow for Xilinx
tools, titled 100 Power Tips for FPGA Designers. <a href="http://www.outputlogic.com">Evgeni
Stavinov</a> is an experienced FPGA designer who
previously worked for Xilinx. It is not evident from the title, but this book
focuses almost entirely on the Xilinx, while …</p>
                    </article>
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                        <h1 class="entry-title"><a href="../debugging-linux-start-up-on-altera-cyclone-v-soc-with-openocd.html">Debugging Linux start-up on Altera Cyclone V SoC with OpenOCD</a></h1>
<div class="post-info">
	<ul>
        <li class="vcard author">
                 by&nbsp;<a class="url fn" href="../author/jan-marjanovic.html">Jan Marjanovic</a>
        </li>
        <li class="published" title="2016-07-12T22:00:00+02:00">
          on&nbsp;Tue 12 July 2016
        </li>

	</ul>
<p>Category: <a href="../tag/fpga.html">FPGA</a>, <a href="../tag/altera.html">Altera</a>, <a href="../tag/linux.html">Linux</a>, <a href="../tag/openocd.html">OpenOCD</a>, </p>
</div><!-- /.post-info --><p>This blog post will show you how one can use the OpenOCD debugger with Altera
Cyclone V SoC. Altera Cyclone V SoC is a very interesting integrated circuit,
combining dual-core ARM processor and a decent FPGA, allowing a wide variety
of possibilities to partition the application between the two.</p>
<p>Xilinx …</p>
                    </article>
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                    <article>
                        <h1 class="entry-title"><a href="../hdl-data-type-for-python-parser-implementations.html">HDL data type for Python parser implementations</a></h1>
<div class="post-info">
	<ul>
        <li class="vcard author">
                 by&nbsp;<a class="url fn" href="../author/jan-marjanovic.html">Jan Marjanovic</a>
        </li>
        <li class="published" title="2015-11-15T22:00:00+01:00">
          on&nbsp;Sun 15 November 2015
        </li>

	</ul>
<p>Category: <a href="../tag/python.html">Python</a>, <a href="../tag/verilog.html">Verilog</a>, <a href="../tag/fpga.html">FPGA</a>, <a href="../tag/hdl.html">HDL</a>, </p>
</div><!-- /.post-info --><p>Recently I had to implement a parser for the PCIe protocol. The data was
captured with Xilinx ChipScope and saved as TSV (tab-separated value) text file.
I wanted to implement a parser in Python, my favorite language for this kind of
tasks. I have stumbled to a problem when I …</p>
                    </article>
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                    <article>
                        <h1 class="entry-title"><a href="../lattice-ice40-configuration-using-raspberry-pi.html">Lattice iCE40 configuration using Raspberry Pi</a></h1>
<div class="post-info">
	<ul>
        <li class="vcard author">
                 by&nbsp;<a class="url fn" href="../author/jan-marjanovic.html">Jan Marjanovic</a>
        </li>
        <li class="published" title="2015-01-18T22:00:00+01:00">
          on&nbsp;Sun 18 January 2015
        </li>

	</ul>
<p>Category: <a href="../tag/lattice.html">Lattice</a>, <a href="../tag/ice40.html">iCE40</a>, <a href="../tag/fpga.html">FPGA</a>, <a href="../tag/raspberry-pi.html">Raspberry Pi</a>, <a href="../tag/bash.html">bash</a>, </p>
</div><!-- /.post-info --><p>As I mentioned in previous post, I started playing around with Lattice iCE40 FPGA. 
In the last post I did a quick overview of the 
iCE40 tools. The iCEcube2 cannot compete with Xilinx ISE and Altera Quartus II, 
not to mention the Vivado, but since this is a low-cost FPGA …</p>
                    </article>
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                    <article>
                        <h1 class="entry-title"><a href="../my-first-encounter-with-lattice-semiconductor.html">My first encounter with Lattice Semiconductor</a></h1>
<div class="post-info">
	<ul>
        <li class="vcard author">
                 by&nbsp;<a class="url fn" href="../author/jan-marjanovic.html">Jan Marjanovic</a>
        </li>
        <li class="published" title="2014-12-24T20:00:00+01:00">
          on&nbsp;Wed 24 December 2014
        </li>

	</ul>
<p>Category: <a href="../tag/lattice.html">Lattice</a>, <a href="../tag/ice40.html">iCE40</a>, <a href="../tag/fpga.html">FPGA</a>, </p>
</div><!-- /.post-info --><p>The FPGA market is one of those classical markets where there are two players 
who have nearly 100% market share, e.g. PC processors (Intel and AMD), graphic
cards (NVIDIA and ATI), ... The two mayor players on the FPGA market are Xilinx
and Altera. Both of this two companies follows …</p>
                    </article>
 
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